IEEE International Conference on High Performance Switching and Routing
17-20 June 2018 – Bucharest, Romania

Program

Day  Time Session/Event
Sunday  08:30 – 9:00  Breakfast
 9:00 – 11:00 Unikraft Hackathon Session 1
 11:00 – 11:30 Coffee Break
 11:30 – 13:00 Unikraft Hackathon Session 2
 13:00 – 14:00 Lunch Break
 14:00 – 15:30 Unikraft Hackathon Session 3
 15:30 – 16:00 Coffee Break
 16:00 – 18:00 P4 Tutorial
 18:30 – 20:30 Welcome Reception
Monday  8:30 – 9:00 Breakfast
 9:00 – 10:00 Keynote 1: DK Panda
 10:00 – 10:45 Paper Session 1: Congestion Control
Fairness in the Data Center – Yi Xi Gong, James Roberts, Dario Rossi (Telecom ParisTech, France)
Revisiting the Theoretical Foundations of Internet Congestion Control – Michael Schapira (Hebrew University) – invited paper
 10:45 – 11:15 Coffee Break
 11:15 – 12:45 Paper Session 2: Packet Processing
Creating Complex Network Services with eBPF: Experience and Lessons Learned – Sebastiano Miano, Matteo Bertrone, Fulvio Risso, Mauricio Vasquez Bernal, Massimo Tumolo (Politecnico di Torino, IT)
Fast Quagga Data Plane Based on Netmap Platform – Hasan Redžović, Aleksandra Smiljanić, Mihailo Vesović (Univ. Belgrade, RS)
Building a chain of high-speed VNFs in no time – Tom Barbette, Cyril Soldani, Romain Gaillard and Laurent Mathy (U. Liege) – invited paper
Toward Fine-grained Load Balancing through RNIC EC Offloading – Xiaoliang Wang, Cam-Tu Nguyen, Baoliu Ye, Zhuzhong Qian, Tang Bin, Wenzhong Li, Sanglu Lu (Nanjing Univ., CN)
 12:45 – 14:00 Lunch break
 14:00 – 15:05 Paper Session 3: Hardware Classification and FPGAs
Multiple Hash Matching Units (MHMU): An Algorithmic Ternary Content Addressable Memory Design for Field Programmable Gate Arrays – Pedro Reviriego (Univ. Antonio de Nebrija), Salvatore Pontarelli (CNIT Roma Tor Vergata), Anees Ullah (Center of Advanced Studies in Engineering, PK), Giuseppe Bianchi (Univ. Roma Tor Vergata); Ali Zahir (COMSATs institute of Information Technology, PK)
Flow Cache Cleansing with FPGA Hash Pipe for Highly Stabilized Software Data Plane – Koji Yamazaki, Yuta Ukon, Shuhei Yoshida, Saki Hatta, Yusuke Sekihara, Shoko Ohteru, Tomoaki Kawamura, Takahiro Hatano, Koyo Nitta, Akihiko Miyazaki (NTT Corp., Japan)
Real-Time Traffic Classification using Simple CART Forest on FPGAs – Tuncay Soylu, Oğuzhan Erdem, Aydın Carus, Edip S. Güner (Trakya University, TR)
 15:05 – 15:30 Coffee break
 15:30 – 17:30 eBPF Tutorial
 19:00 – 20:00 Walking Tour (Historic Center)
Tuesday  8:30 – 9:00 Breakfast
 9:00 – 10:00 Keynote 2: Raj Jain
 10:00 – 10:45 Paper Session 4: Programmable Hardware (I)
The Programmable Data Plane: Abstractions, Architectures, and Open Problems – Roberto Bifulco (NEC Research Europe), Gabor Retvari (BME Hungary) – invited paper
Beyond SmartNICs: Towards a Fully Programmable Cloud – Adrian Caulfield, Paolo Costa, Monia Ghobadi (Microsoft Research) – invited paper
 10:45 – 11:15 Coffee break
 11:15 – 12:45 Paper Session 5: Optical Networks
Toward Optical Switching in the Data Center – William M. Mellette, Alex C. Snoeren, and George Porter (UCSD) – invited paper
Redefining the Economics of Reach with Integrated Optics – Cyriel Minkenberg, German Rodriguez, Nick Kucharewski (Rockley Photonics) – invited paper
40 Gb/s Short Range Optical Interconnects with 8ns Power-on and CDR-Lock Time in 14nm CMOS – T. Morf, A. Cevrero, I. Ozkaya, P. Francese, L. Y. Chen, C. Menolfi, M. Kossel M. Braendli, M. Seifried, L. Kull, D. Luu, and T.Toifl (IBM Research, EPFL, ETH) – invited paper
Dynamic Spectrum Sharing Method in SDM based Optical Packet and Circuit Integrated Networks – Ken Nagatomi (Osaka Univ.), Yusuke Hirota (NICT), Hideki Tode (Osaka Prefecture Univ.), Takashi Watanabe (Osaka Univ.)
 12:45 – 14:00 Lunch break
 14:00 – 15:00 Panel Discussion
 15:00 – 15:30 Coffee Break
 15:30 – 17:30 Mellanox Tutorial on SmartNICs
 19:30 – 23:00 Conference Banquet
Wednesday  08:30 – 09:00 Breakfast
 09:00 – 10:00 Keynote 3: Bruce Maggs – Internet at the Speed of Light
 10:00 – 10:45 Paper Session 6: Programmable Hardware (II)
A Programmable Hardware Calendar for High Resolution Pacing – Salvatore Pontarelli (CNIT, Roma Tor Vergata), Giuseppe Bianchi (Univ. Roma Tor Vergata), Michael Welzl (Univ. Oslo)
T4P4S: A Target-independent Compiler for Protocol-independent Packet Processors – Péter Vörös, Dániel Horpácsi, Róbert Kitlei, Dániel Leskó, Máté Tejfel, Sándor Laki (ELTE Eötvös Loránd Univ., HU)
 10:45 – 11:15 Coffee Break
 11:15 – 12:45 Paper Session 7: Routing and Scheduling
Scheduling Mixed Unicast and Multicast Traffic with Variable-Size Packets in Input-Queued Switches – Jie Xiao (Univ. Hong Kong), Kwan Yeung (Univ. Hong Kong), Sugih Jamin (Univ. Michigan)
A New Scheduling Algorithm for Input-Queued Switches with Mixed Unicast and Multicast Traffic – Jie Xiao (Univ. Hong Kong), Kwan Yeung (Univ. Hong Kong), Sugih Jamin (Univ. Michigan)
Backup Network Design Scheme for Multiple Link Failures to Avoid Overestimating Link Capacity – Yuki Hirano, Fujun He, Takehiro Sato, Eiji Oki (Kyoto Univ., Japan)
Efficient Make Before Break Capacity Defragmentation – Huy Duong Quang (Concordia University), Brigitte Jaumard (Concordia University), David Coudert (INRIA), Ron Armolavicius (CIENA)
 12:45 – 14:00  Lunch break
 15:00 – 17:00  Visit Palace of Parliament