Network research has traditionally been divided across the software and hardware gap of two communities. The Computer Science community has focused on the higher layers of the protocol stack, while assuming best-effort packet forwarding offered by the switch/router ASICs. Orthogonal efforts in the Electrical Engineering community have advanced the switch/router hardware to support ever-increasing raw speeds across a multitude of physical channels. This simple packet forwarding API has helped shield one community from the other, and has lead to unbelievable success.
However, this API is quickly becoming obsolete. The emerging software-defined networking (SDN) and network function virtualization (NFV) trends have provided a compelling approach towards a smarter and more flexible (software-based) networking. Still, the performance of software-based networks leveraging general-purpose computer architectures is below par, especially considering the expected increases in traffic volumes and amount of connected endpoints. These challenges can be addressed via novel approaches that leverage hardware-software co-design techniques, or exploit currently emerging high-performance programmable data planes or fast network processing frameworks, such as P4, NetFPGA, OpenState, etc.
IEEE HPSR 2018 aims to collect contributions and visions from both the hardware (e.g., Electrical Engineering) and the software (e.g., Computer Science) communities, and bridge the traditional gap between hardware and software. The focus of the conference is to achieve a unified view of the hardware implementation challenges facing programmable packet-processing pipelines (such as, but not limited, to P4, OpenState, etc) and understanding the tradeoff between deployability and processing flexibility. Finally, we seek to understand novel processing needs stemming from the Computer Science community (e.g., network functions) and whether these can be efficiently supported in programmable hardware.
Examples of research areas considered in IEEE HPSR 2018
- Architectures of high-performance switches and routers, with a focus towards reconfigurable pipelines (P4, Openflow, etc).
- High-speed packet processors.
- Trade-off between deployability in hardware and processing flexibility.
- Address lookup algorithms, packet classification, scheduling, and dropping.
- Applications of high performance, programmable networks including but not limited to network function virtualization, the Internet of things and Next Generation Internet.
- Efficient data structures for networking applications.
- Switching, bridging, and routing protocols whether wide-area or data centers.
- Optical switching and routing.
- Software defined networking.
- Multiprocessor networks.
- Network management.
- Traffic characterization and engineering.
- Power-aware switching, bridging, and routing protocols.
- Network security.
- Virtualized network functions (e.g., firewalls, intrusion detection systems, load balancers, etc.) built or managed using software-defined networks.
Submitted papers must be unpublished and should not be submitted elsewhere at the same time. Accepted papers should not exceed 6 pages in two-column IEEE Transactions style. Accepted papers longer than 6 pages will be charged for each extra page. Papers cannot be longer than 8 pages. Papers should be submitted as PDF files through the Microsoft CMT system. All submitted papers will be subject to three independent reviews.
To be published in the IEEE HPSR 2018 Conference Proceedings and to be eligible for publication in IEEE Xplore®, an author of an accepted paper is required to register for the conference at the full (member or non-member) rate and the paper must be presented by an author of that paper at the conference unless the TPC Chairs grant permission for a substitute presenter arranged in advance of the event and who is qualified both to present and answer questions. Non-refundable registration fees must be paid prior to uploading the final IEEE formatted, publication-ready version of the paper. For authors with multiple accepted papers, one full registration is valid for up to 2 papers.
IEEE and IEEE Communications Society Policies
To ensure appropriate consideration of conflicts of interest during the review process, the ComSoc prohibits changes to the list of authors once a paper has been submitted for review during review, revision, or (if accepted) final publication. The author list may be changed only prior to the submission deadline.
Paper submission due: March 2, 2018 March 19, 2018, 9:00 AM CET (extended)
Acceptance notifications: April 25, 2018 Final version submission deadline: May 15, 2018
- Author registration (discounted fees): May 31, 2018
- Author registration deadline: May 31, 2018
- Conference date: June 17-20, 2018
Tutorial Proposal Submission
Proposal submission due: March 5, 2018 Acceptance notification: April 3, 2018 Tutorial slides/notes submission due: April 27, 2018
- Tutorial date: June 17, 2018
Conference Location: Bucharest, Romania
Bucharest is the capital of Romania, the largest eastern European country with 20 million inhabitants and a surface similar to the UK. To many foreigners Romania is famous for its Count Dracula, a legend written by Bram Stoker based on the cruel Valachian ruler Vlad Tepes (i.e., the Impaler , in power 1431-1476). Bucharest has around 3 million inhabitants and has a booming economy, rich cultural scene and a vibrant lifestyle. Bucharest has earned the nickname of “Little Paris” in the early 20th century due to its French-inspired architecture and its numerous landmarks. The conference will be held in the campus of University Politehnica of Bucharest, the top engineering school in Romania and a source of leading computer scientists worldwide.