Network research has traditionally been divided across the software and hardware gap of two communities. The Computer Science community has focused on the higher layers of the protocol stack, while assuming best-effort packet forwarding offered by the switch/router ASICs. Orthogonal efforts in the Electrical Engineering community have advanced the switch/router hardware to support ever-increasing raw speeds across a multitude of physical channels. This simple packet forwarding API has helped shield one community from the other, and has lead to unbelievable success.
However, this API is quickly becoming obsolete. The emerging software-defined networking (SDN) and network function virtualization (NFV) trends have provided a compelling approach towards a smarter and more flexible (software-based) networking. Still, the performance of software-based networks leveraging general-purpose computer architectures is below par, especially considering the expected increases in traffic volumes and amount of connected endpoints. These challenges can be addressed via novel approaches that leverage hardware-software co-design techniques, or exploit currently emerging high-performance programmable data planes or fast network processing frameworks, such as P4, NetFPGA, OpenState, etc.
IEEE HPSR 2018 aims to collect contributions and visions from both the hardware (e.g., Electrical Engineering) and the software (e.g., Computer Science) communities, and bridge the traditional gap between hardware and software. The focus of the conference is to achieve a unified view of the hardware implementation challenges facing programmable packet-processing pipelines (such as, but not limited, to P4, OpenState, etc) and understanding the tradeoff between deployability and processing flexibility. Finally, we seek to understand novel processing needs stemming from the Computer Science community (e.g., network functions) and whether these can be efficiently supported in programmable hardware.
Examples of research areas considered in IEEE HPSR 2018 include:
- Architectures of high-performance switches and routers, with a focus towards reconfigurable pipelines (P4, Openflow, etc).
- High-speed packet processors.
- Trade-off between deployability in hardware and processing flexibility.
- Address lookup algorithms, packet classification, scheduling, and dropping.
- Applications of high performance, programmable networks including but not limited to network function virtualization, the Internet of things and Next Generation Internet.
- Efficient data structures for networking applications.
- Switching, bridging, and routing protocols whether wide-area or data centers.
- Optical switching and routing.
- Software defined networking.
- Multiprocessor networks.
- Network management.
- Traffic characterization and engineering.
- Power-aware switching, bridging, and routing protocols.
- Network security.
- Virtualized network functions (e.g., firewalls, intrusion detection systems, load balancers, etc.) built or managed using software-defined networks.
CONFERENCE LOCATION: Bucharest, Romania
Bucharest is the capital of Romania, the largest eastern European country with 20 million inhabitants and a surface similar to the UK. To many foreigners Romania is famous for its Count Dracula, a legend written by Bram Stoker based on the cruel valachian ruler Vlad Tepes (i.e., the Impaler , in power 1431-1476). Bucharest has around 3 million inhabitants and has a booming economy, rich cultural scene and a vibrant lifestyle. Bucharest has earned the nickname of “Little Paris” in the early 20th century due to its French-inspired architecture and its numerous landmarks. The conference will be held in the campus of University Politehnica of Bucharest, the top engineering school in Romania and a source of leading computer scientists worldwide.