Dhabaleswar K. (DK) Panda is a Professor and Distinguished Scholar of Computer Science at the Ohio State University and a Fellow of IEEE. His research includes parallel computer architecture, high-performance networking, InfiniBand, network-based computing, exascale computing, programming models, GPUs and accelerators, high-performance file systems and storage, virtualization and cloud computing and Big Data. He has published over 400 papers in major journals and conferences. Dr. Panda leads the Network-Based Computing Research Group . Members of his group have obtained a large number of Awards and Recognitions . Students and staff members of this group are involved in multiple state-of-the-art research projects. Dr. Panda and his research group members have been doing extensive research on modern networking technologies including InfiniBand, Omni-Path, iWARP and RoCE. His research group is currently collaborating with national laboratories and leading InfiniBand, Omni-Path, iWARP and RoCE companies. The MVAPICH (High Performance MPI and MPI+PGAS over InfiniBand, iWARP and RoCE with support for GPGPUs, Xeon Phis and Virtualization) software libraries, developed by his research group, are currently being used by more than 2,850 organizations in 85 countries. Multiple software libraries for Big Data processing and management, designed and developed by the group under the High-Performance Big Data (HiBD) project are available. The group has also been focusing on co-designing Deep Learning Frameworks and MPI Libraries. A high-performance and scalable version of the Caffe framework is available from High-Performance Deep Learning (HiDL) project site. Dr. Panda’s research is supported by funding from US NSF, DoE, Ohio Board of Regents and several companies including IBM, Intel, Cisco, Cray, SUN, Mellanox, Microsoft, NVIDIA, QLogic and NetApp. Further information about Dr. Panda can be found at: http://web.cse.ohio-state.edu/~panda.2/, https://insidehpc.com/2017/05/rock-stars-hpc-dk-panda/ and https://insidehpc.com/2016/11/high-performance-deep-learning/.
Submitted papers must be unpublished and should not be submitted elsewhere at the same time. Accepted papers should not exceed 6 pages in two-column IEEE Transactions style. Accepted papers longer than 6 pages will be charged for each extra page. Papers cannot be longer than 8 pages. Papers should be submitted as PDF files through the Microsoft CMT system. All submitted papers will be subject to three independent reviews.
To be published in the IEEE HPSR 2018 Conference Proceedings and to be eligible for publication in IEEE Xplore®, an author of an accepted paper is required to register for the conference at the full (member or non-member) rate and the paper must be presented by an author of that paper at the conference unless the TPC Chairs grant permission for a substitute presenter arranged in advance of the event and who is qualified both to present and answer questions. Non-refundable registration fees must be paid prior to uploading the final IEEE formatted, publication-ready version of the paper. For authors with multiple accepted papers, one full registration is valid for up to 2 papers.
IEEE and IEEE Communications Society Policies
To ensure appropriate consideration of conflicts of interest during the review process, the ComSoc prohibits changes to the list of authors once a paper has been submitted for review during review, revision, or (if accepted) final publication. The author list may be changed only prior to the submission deadline.
- Paper submission due:
March 2, 2018March 19, 2018, 9:00 AM CET (extended)
- Acceptance notifications: April 23, 2018
- Final version submission deadline: May 15, 2018
- Author registration (discounted fees): May 16, 2018
- Author registration deadline: May 18, 2018
- Conference date: June 17-20, 2018
Innova2 Tutorial: An Industrial Strength Capable FPGA +NIC Platform
Data Centers, Machine Learning platforms and 5G infrastructure present significant challenges to the network infrastructure, including bandwidth and latency as well as power and cost. It is long known that FPGAs provide the ultimate programmability in close to hardware cost. Tight integration of the silicon accelerators, like RDMA and encryption, provided by modern NICs with FPGA flexibility has a great potential to meet these challenges. But Bump on the Wire Architecture does not meet the NFV requirements as the FPGA has to be aware of all the VM flow control rules, which get updated very fast.
Mellanox invented Innova®2 which allows the FPGA to offload virtual networks and virtual machines, without the need to parse and update the FPGA about the packet header. In this tutorial, we will present the Mellanox Innova®2 FPGA+NIC integrated board and teach you how to build the future network-edge applications on top of it. The tutorial covers the architecture, the principles of operations, and the development environment.
The tutorial will include two practical examples as follows:
- Catch a specific vflow in FPGA without a single line of FPGA coding.
- Modify the flow packets in the FPGA.
Dotan Levi is a senior architect at Mellanox Technologies. He has 13 years of experience, spread across software, hardware, algorithms and architectures. In the past Dotan worked for Zoran Semiconductor (later acquired by CSR) doing algorithms and architectures. Dotan holds a B.Sc degree in Electrical Engineering from Technicon Israel Institute of Technology.
Toward Flexible and Efficient In-Kernel Network Function Chaining with IOVisor
The eBPF Linux module, which represents the main component of the IOVisor technology, became part of the Linux kernel in 2013. This module enables arbitrary code to be dynamically injected and executed in the Linux kernel while at the same time providing hard safety guarantees in order to preserve the integrity of the system.
While, so far, this component has been used mainly for tracing, monitoring and statistics (in fact, several tools exist that extract information from network traffic and other kernel events such as page faults, system calls, and more), recent projects proposed its usage also for the creation of complex network functions.
This tutorial focuses on the high performance network processing capabilities of IOVisor and it presents the state of the art of the above technology, including XDP (eXpress Data Path), which enables a vanilla Linux kernel to sustain a 10Gbps wire-rate throughput. In addition, it presents the recent extensions of the Iovisor technology that allow the creation of complex network functions (switch, router, NAT, load balancer, firewall, etc.), including both data and control plane. This enables the creation of arbitrary modules, dynamically injectable at run-time, which can be used to create complex service chains and datacenter-wide services (such as the Cilium project).
Finally, this tutorial will summarize the possible interactions of IOVisor with other emerging technologies, such as OpenFlow/OpenState, P4, and SmartNICs.
Fulvio Risso (Ph.D. in Computer Engineering) is Associate Professor at the Department of Control and Computer Engineering of Politecnico di Torino, Italy. His research interests focus on high-speed and flexible network processing, software-defined networks, and network functions virtualization. He started and led several open-source software projects including WinPcap, the de-facto library for capturing and analyzing traffic on Windows. Fulvio is author of 100+ scientific papers, mostly focused on high-speed and flexible network processing.
Network research has traditionally been divided across the software and hardware gap of two communities. The Computer Science community has focused on the higher layers of the protocol stack, while assuming best-effort packet forwarding offered by the switch/router ASICs. Orthogonal efforts in the Electrical Engineering community have advanced the switch/router hardware to support ever-increasing raw speeds across a multitude of physical channels. This simple packet forwarding API has helped shield one community from the other, and has lead to unbelievable success.
However, this API is quickly becoming obsolete. The emerging software-defined networking (SDN) and network function virtualization (NFV) trends have provided a compelling approach towards a smarter and more flexible (software-based) networking. Still, the performance of software-based networks leveraging general-purpose computer architectures is below par, especially considering the expected increases in traffic volumes and amount of connected endpoints. These challenges can be addressed via novel approaches that leverage hardware-software co-design techniques, or exploit currently emerging high-performance programmable data planes or fast network processing frameworks, such as P4, NetFPGA, OpenState, etc.
IEEE HPSR 2018 aims to collect contributions and visions from both the hardware (e.g., Electrical Engineering) and the software (e.g., Computer Science) communities, and bridge the traditional gap between hardware and software. The focus of the conference is to achieve a unified view of the hardware implementation challenges facing programmable packet-processing pipelines (such as, but not limited, to P4, OpenState, etc) and understanding the tradeoff between deployability and processing flexibility. Finally, we seek to understand novel processing needs stemming from the Computer Science community (e.g., network functions) and whether these can be efficiently supported in programmable hardware.
Examples of research areas considered in IEEE HPSR’18
- Architectures of high-performance switches and routers, with a focus towards reconfigurable pipelines (P4, Openflow, etc).
- High-speed packet processors.
- Trade-off between deployability in hardware and processing flexibility.
- Address lookup algorithms, packet classification, scheduling, and dropping.
- Applications of high performance, programmable networks including but not limited to network function virtualization, the Internet of things and Next Generation Internet.
- Efficient data structures for networking applications.
- Switching, bridging, and routing protocols whether wide-area or data centers.
- Optical switching and routing.
- Software defined networking.
- Multiprocessor networks.
- Network management.
- Traffic characterization and engineering.
- Power-aware switching, bridging, and routing protocols.
- Network security.
- Virtualized network functions (e.g., firewalls, intrusion detection systems, load balancers, etc.) built or managed using software-defined networks.
Conference Location: Bucharest, Romania
Bucharest is the capital of Romania, the largest eastern European country with 20 million inhabitants and a surface similar to the UK. To many foreigners Romania is famous for its Count Dracula, a legend written by Bram Stoker based on the cruel Valachian ruler Vlad Tepes (i.e., the Impaler , in power 1431-1476). Bucharest has around 3 million inhabitants and has a booming economy, rich cultural scene and a vibrant lifestyle. Bucharest has earned the nickname of “Little Paris” in the early 20th century due to its French-inspired architecture and its numerous landmarks. The conference will be held in the campus of University Politehnica of Bucharest, the top engineering school in Romania and a source of leading computer scientists worldwide.