The program overview of HPSR’18 and the list of accepted papers are available here.
SmartNICs provide tight integration of compute power with the NIC hardware offloads for RDMA, steering, packet processing and security accelerators. It also enables software services to run transparently and in isolation from the host CPU on the network edge. These two SmartNICs properties enables a new class of data-center applications including Network Edge Security, Storage Virtualization, Bare Metal Clouds, SLA Monitoring and more.
Data-center security has been forced to reinvent itself as software complexity increases, networking capabilities grow more agile, and attack complexity turns unmanageable. With this change, the need for security policy enforcement to be handled at the edge has pushed functionality onto host compute systems, resulting in inherent performance loss and security weakness due to consolidation of resources. SmartNICs solve both the performance problem and the security problem of edge-centric policy models.
This tutorial will cover the architecture, principles of operation, and development flow of the Mellanox BlueField SmartNIC. The tutorial will include examples showing the difference between a NIC and a SmartNIC packet flow manipulation within the SmartNIC basic security operations and offloads security orchestration and policy enforcement.
Date and Time
Tuesday, June 19th, from 16:00 to 18:00
Jack Matheson is a principal architect at Mellanox Technologies, where he is responsible for the development of technology to make data-centers more secure. For 15 years, he has been building software/hardware hybrid solutions to help accelerate and secure workloads – most recently at McAfee, where he was the chief cloud architect for enterprise security, and Intel, as the software architect for cloud identity.
Tutorial on P4, a Language for the Future Programmable Network Devices
P4 (p4.org) is a candidate language for the future programmable network devices that can be used for describing how network packets should be processed on a variety of hardware targets ranging from general-purpose CPUs to custom ASICs. Its main goals are 1) protocol independence: devices are not tied to existing protocols and new headers can be introduced easily; 2) reconfigurability: the behavior of the devices can be modified in run-time and 3) portability: the P4 program is independent of the hardware target. The packet processing model of P4 is quite similar to how OpenFlow works. There is a parsing phase at the beginning and a deparsing phase at the end. The former phase extracts the packet header structures and the contained data for further processing, the latter phase rebuilds the headers before sending out. The business logic is between these two phases, implementing a series of lookups in predefined match/action tables, branching on whether the lookup resulted in a hit or a miss. The real power of P4 lies here, describing these tables, lookups, and actions in an abstract, straightforward manner with the freedom of defining any kind of protocol headers.
Since its creation in 2013, P4 has been gaining adoption at an exponential rate, rapidly becoming the standard way to describe packet processing pipelines. The potential of the language to describe common networking tasks has already been showcased by some preliminary works. Today, a hectic ecosystem of open source software tools is maintained and developed by the P4 community. The P4 community has created—and continues to maintain and develop—a language specification, a set of open-source tools (compilers, debuggers, code analyzers, libraries, software P4 switches, etc.), and sample P4 programs with the goal of making it easy for P4 users to quickly and correctly author new data-plane behaviors. On 16th March it was announced that P4 will become a project of the Open Networking Foundation (ONF) and the Linux Foundation portfolio.
This half-day tutorial will introduce the audience to the latest version of P4 language (P4-16), providing attendees with the required knowledge to start developing and prototyping their own ideas on data plane logic. After introducing some basic examples including L2 forwarding and L3 routing, more complex use cases like BNG, mobile GW and VXLAN-based data center GW will be presented in a hands-on training session using available P4 development tools and compilers.
The tutorial will be useful to researchers, students, and practitioners from network admins and network architects to developers. Attendees are expected to bring their own laptops since we will provide a pre-configured VM image containing all necessary open-source tools and P4 programs. We advise the participants to pre-install. Approximately 10GB of free disk space is required for the virtual machine.
Date and Time
Sunday, June 17th, from 16:00 to 18:00
P Gyanesh Kumar Patra – Ph.D. candidate at University of Campinas, Brazil. His primary interests are in SDN and programmable dataplane. He has nearly five years of industry experience working on network operating systems, data center protocol like QCN, SPB, etc. He also worked as a visiting researcher at Ericsson Research, Hungary. Currently, he is pursuing his thesis on building cross-platform software switch for programmable dataplanes.
Péter Vörös – ELTE Eötvös Loránd University, Budapest, Hungary (Communication Networks Laboratory) Péter Vörös received the MSc degree and graduated in the doctoral school in computer science from the Eötvös Loránd University,
Budapest, Hungary, in 2014, and 2017 respectively. He is currently a doctoral candidate and working as an assistant lecturer at the Department of Information Systems, Eötvös Loránd University. He is recently working on projects in the topics of network security, traffic analytics and programmable data planes. He is one of the developers of the open-source multi-target P4 compiler called T4P4S.
Sándor Laki – ELTE Eötvös Loránd University, Budapest, Hungary (Communication Networks Laboratory) Sándor Laki received the MSc and PhD degrees in computer science from the Eötvös Loránd University, Budapest, Hungary, in 2007 and 2015, respectively. He is currently working as an assistant professor at the Department of Information Systems, Eötvös Loránd University. His research interests focus on active and passive network measurement techniques, traffic analytics, resource sharing, programmable data planes and their application for new networking solutions. He is the author of more than 25 peer-reviewed papers and demo papers including publications at JSAC, INFOCOM, ICC and SIGCOMM. He is one of the key contributors of the open-source multi-target P4 compiler development project called T4P4S.
Bruce Maggs received the S.B., S.M., and Ph.D. degrees in Computer Science from the Massachusetts Institute of Technology (MIT) in 1985, 1986, and 1989, respectively. His advisor was Charles Leiserson. After spending one year as a Post-doctoral Associate at MIT, he worked at NEC Research Institute in Princeton from 1990 to 1993. In 1994, he moved to Carnegie Mellon, where he stayed until 2009. While on a two-year leave-of-absence from Carnegie Mellon, Maggs helped launch Akamai Technologies, serving as its first Vice President for Research and Development. He retains a part-time role at Akamai as Vice President for Research. Maggs is now is the Pelham Wilder Professor of Computer Science at Duke University.
Maggs’s research focuses on networking, distributed systems, and security. In 1986, he became the first winner (with Charles Leiserson) of the Daniel L. Slotnick Award for Most Original Paper at the International Conference on Parallel Processing, and in 1994 he received an NSF National Young Investigator Award. He was co-chair of the 1993-1994 DIMACS Special Year on Massively Parallel Computation and has served on the steering committees for the ACM Symposium on Parallel Algorithms and Architectures (SPAA), the ACM Internet Measurement Conference (IMC), and the ACM HotNets Conference. He has served on the program committees of numerous conferences including STOC, SODA, PODC, NSDI, and SIGCOMM. In 2017 he was a co-recipient of the IEEE Cybersecurity Innovation Award, a Distinguished Paper Award at USENIX Security, the Best Dataset Award at the Passive and Active Measurement Conference, and the Best Paper Award at CoNEXT.
Dhabaleswar K. (DK) Panda is a Professor and Distinguished Scholar of Computer Science at the Ohio State University and a Fellow of IEEE. His research includes parallel computer architecture, high-performance networking, InfiniBand, network-based computing, exascale computing, programming models, GPUs and accelerators, high-performance file systems and storage, virtualization and cloud computing and Big Data. He has published over 400 papers in major journals and conferences. Dr. Panda leads the Network-Based Computing Research Group . Members of his group have obtained a large number of Awards and Recognitions . Students and staff members of this group are involved in multiple state-of-the-art research projects. Dr. Panda and his research group members have been doing extensive research on modern networking technologies including InfiniBand, Omni-Path, iWARP and RoCE. His research group is currently collaborating with national laboratories and leading InfiniBand, Omni-Path, iWARP and RoCE companies. The MVAPICH (High Performance MPI and MPI+PGAS over InfiniBand, iWARP and RoCE with support for GPGPUs, Xeon Phis and Virtualization) software libraries, developed by his research group, are currently being used by more than 2,850 organizations in 85 countries. Multiple software libraries for Big Data processing and management, designed and developed by the group under the High-Performance Big Data (HiBD) project are available. The group has also been focusing on co-designing Deep Learning Frameworks and MPI Libraries. A high-performance and scalable version of the Caffe framework is available from High-Performance Deep Learning (HiDL) project site. Dr. Panda’s research is supported by funding from US NSF, DoE, Ohio Board of Regents and several companies including IBM, Intel, Cisco, Cray, SUN, Mellanox, Microsoft, NVIDIA, QLogic and NetApp. Further information about Dr. Panda can be found at: http://web.cse.ohio-state.edu/~panda.2/, https://insidehpc.com/2017/05/rock-stars-hpc-dk-panda/ and https://insidehpc.com/2016/11/high-performance-deep-learning/.
Submitted papers must be unpublished and should not be submitted elsewhere at the same time. Accepted papers should not exceed 6 pages in two-column IEEE Transactions style. Accepted papers longer than 6 pages will be charged for each extra page. Papers cannot be longer than 8 pages. Papers should be submitted as PDF files through the Microsoft CMT system. All submitted papers will be subject to three independent reviews.
To be published in the IEEE HPSR 2018 Conference Proceedings and to be eligible for publication in IEEE Xplore®, an author of an accepted paper is required to register for the conference at the full (member or non-member) rate and the paper must be presented by an author of that paper at the conference unless the TPC Chairs grant permission for a substitute presenter arranged in advance of the event and who is qualified both to present and answer questions. Non-refundable registration fees must be paid prior to uploading the final IEEE formatted, publication-ready version of the paper. For authors with multiple accepted papers, one full registration is valid for up to 2 papers.
IEEE and IEEE Communications Society Policies
To ensure appropriate consideration of conflicts of interest during the review process, the ComSoc prohibits changes to the list of authors once a paper has been submitted for review during review, revision, or (if accepted) final publication. The author list may be changed only prior to the submission deadline.
Paper submission due: March 2, 2018 March 19, 2018, 9:00 AM CET (extended)
Acceptance notifications: April 25, 2018
- Final version submission deadline: May 15, 2018
- Author registration (discounted fees): May 16, 2018
- Author registration deadline: May 18, 2018
- Conference date: June 17-20, 2018
Toward Flexible and Efficient In-Kernel Network Function Chaining with IOVisor
The eBPF Linux module, which represents the main component of the IOVisor technology, became part of the Linux kernel in 2013. This module enables arbitrary code to be dynamically injected and executed in the Linux kernel while at the same time providing hard safety guarantees in order to preserve the integrity of the system.
While, so far, this component has been used mainly for tracing, monitoring and statistics (in fact, several tools exist that extract information from network traffic and other kernel events such as page faults, system calls, and more), recent projects proposed its usage also for the creation of complex network functions.
This tutorial focuses on the high performance network processing capabilities of IOVisor and it presents the state of the art of the above technology, including XDP (eXpress Data Path), which enables a vanilla Linux kernel to sustain a 10Gbps wire-rate throughput. In addition, it presents the recent extensions of the Iovisor technology that allow the creation of complex network functions (switch, router, NAT, load balancer, firewall, etc.), including both data and control plane. This enables the creation of arbitrary modules, dynamically injectable at run-time, which can be used to create complex service chains and datacenter-wide services (such as the Cilium project).
Finally, this tutorial will summarize the possible interactions of IOVisor with other emerging technologies, such as OpenFlow/OpenState, P4, and SmartNICs.
Date and Time
Monday, June 18th, from 16:00 to 18:00
Fulvio Risso (Ph.D. in Computer Engineering) is Associate Professor at the Department of Control and Computer Engineering of Politecnico di Torino, Italy. His research interests focus on high-speed and flexible network processing, software-defined networks, and network functions virtualization. He started and led several open-source software projects including WinPcap, the de-facto library for capturing and analyzing traffic on Windows. Fulvio is author of 100+ scientific papers, mostly focused on high-speed and flexible network processing.
Network research has traditionally been divided across the software and hardware gap of two communities. The Computer Science community has focused on the higher layers of the protocol stack, while assuming best-effort packet forwarding offered by the switch/router ASICs. Orthogonal efforts in the Electrical Engineering community have advanced the switch/router hardware to support ever-increasing raw speeds across a multitude of physical channels. This simple packet forwarding API has helped shield one community from the other, and has lead to unbelievable success.
However, this API is quickly becoming obsolete. The emerging software-defined networking (SDN) and network function virtualization (NFV) trends have provided a compelling approach towards a smarter and more flexible (software-based) networking. Still, the performance of software-based networks leveraging general-purpose computer architectures is below par, especially considering the expected increases in traffic volumes and amount of connected endpoints. These challenges can be addressed via novel approaches that leverage hardware-software co-design techniques, or exploit currently emerging high-performance programmable data planes or fast network processing frameworks, such as P4, NetFPGA, OpenState, etc.
IEEE HPSR 2018 aims to collect contributions and visions from both the hardware (e.g., Electrical Engineering) and the software (e.g., Computer Science) communities, and bridge the traditional gap between hardware and software. The focus of the conference is to achieve a unified view of the hardware implementation challenges facing programmable packet-processing pipelines (such as, but not limited, to P4, OpenState, etc) and understanding the tradeoff between deployability and processing flexibility. Finally, we seek to understand novel processing needs stemming from the Computer Science community (e.g., network functions) and whether these can be efficiently supported in programmable hardware.
Examples of research areas considered in IEEE HPSR’18
- Architectures of high-performance switches and routers, with a focus towards reconfigurable pipelines (P4, Openflow, etc).
- High-speed packet processors.
- Trade-off between deployability in hardware and processing flexibility.
- Address lookup algorithms, packet classification, scheduling, and dropping.
- Applications of high performance, programmable networks including but not limited to network function virtualization, the Internet of things and Next Generation Internet.
- Efficient data structures for networking applications.
- Switching, bridging, and routing protocols whether wide-area or data centers.
- Optical switching and routing.
- Software defined networking.
- Multiprocessor networks.
- Network management.
- Traffic characterization and engineering.
- Power-aware switching, bridging, and routing protocols.
- Network security.
- Virtualized network functions (e.g., firewalls, intrusion detection systems, load balancers, etc.) built or managed using software-defined networks.
Conference Location: Bucharest, Romania
Bucharest is the capital of Romania, the largest eastern European country with 20 million inhabitants and a surface similar to the UK. To many foreigners Romania is famous for its Count Dracula, a legend written by Bram Stoker based on the cruel Valachian ruler Vlad Tepes (i.e., the Impaler , in power 1431-1476). Bucharest has around 3 million inhabitants and has a booming economy, rich cultural scene and a vibrant lifestyle. Bucharest has earned the nickname of “Little Paris” in the early 20th century due to its French-inspired architecture and its numerous landmarks. The conference will be held in the campus of University Politehnica of Bucharest, the top engineering school in Romania and a source of leading computer scientists worldwide.